1. Field of the Invention
The present invention relates to a Semiconductor storage device of first-in first-out system (hereinafter referred to as a FIFO device).
2. Description of the Background Art
A FIFO device is incorporated in a transmission system for digital data, for example, to perform FIFO processing. In the FIFO processing, transmitted data are stored and the stored data are sent out in the order in which the data were transferred, which is performed in accordance with a clock, as shown in FIG. 6, for example.
FIG. 6 is a block diagram for explaining the outline of a FIFO device used for the purpose of FIFO processing of data in a digital transmission system. In FIG. 6, the FIFO device 1 mediates between a source circuit 2 and a destination circuit 3 in transmission of data.
The FIFO device 1 is supplied with a clock clk from a clock generator 4 and receives a reset signal rst from a reset signal generating circuit 5. The FIFO device 1 includes a random access memory (hereinafter referred to as a RAM) 6 for storing the transmitted data, a read counter portion 7 for generating read addresses used in the RAM 6 and a write counter portion 8 for generating write addresses used in the RAM 6.
FIG. 7 shows an example of relation among the read address RA, the write address WA, the read data dout and the write data din.
In the data stored in the RAM 6, data at the read address RA which is given at the time t1 at which the clock clk falls is read as the data dout and the data din transferred from the source circuit 2 is written into the write address WA which is given to the RAM 6 at the time t2 at which the clock clk rises.
The write counter portion 8 is set so that it provides an output value which is smaller by one than the output value from the read counter portion 7, for example. In this case, with the next clock, an access can be made to the write address equal to the read address with which the data was read, so that the data read from the RAM 6 can be written in an earlier-first order.
Next, referring to FIG. 8 and FIG. 9, configurations of the write counter portion 8 and the read counter portion 7 will be described for the case in which the number of data stored in the FIFO device is a power of 2. For example, the write counter portion 8 includes a D flip-flop 10 and an inverter 20 for dividing the clock clk by 2, a half adder 11 for adding the output of the D flip-flop 10 obtained by dividing the clock clk by 2 and the sum output provided by itself one clock earlier, a half adder 12 for adding the carry output of the half adder 11 and the one-clock-earlier sum output of itself, a half adder 13 for adding the carry output of the half adder 12 and the one-clock-earlier sum output of itself, D flip-flops 17-19 for respectively holding the sum outputs of the corresponding half adders 11-13, and four AND gates 21, 14-16 for respectively resetting the corresponding D flip-flops 10, 17-19. The output of the write counter portion 8 is 4 bits.
The reset signal rst is provided to the input terminal 23 and the clock clk is provided to the input terminal 22. The output value of the write counter portion 8 is outputted from the output terminal 24 as the write address.
The output of the AND gate 21 obtained from the AND of the reset signal rst and the output of the inverter 20 is captured as data for the D flip-flop 10. The inverter 20 inverts the output from the D flip-flop 10. The AND gates 14-16 are all supplied with the reset signal rst at their respective inputs on one side, and with the outputs from the corresponding half adders 11-13 at their respective inputs on the other side.
The read counter portion 7, for example, includes a D flip-flop 30, an NAND gate 42, and inverters 40, 41 for dividing the clock clk by 2, a half adder 31 for adding the output of the D flip-flop 30 obtained by dividing the clock clk by 2 and the sum output provided by itself one clock earlier, a half adder 32 for adding the carry output of the half adder 31 and the one-clock-earlier sum output of itself, a half adder 33 for adding the carry output of the half adder 32 and the one-clock-earlier sum output of itself, D flip-flops 37-39 for respectively holding the sum outputs of the corresponding half adders 31-33, and four AND gates 42, 34-36 for respectively resetting the corresponding D flip-flops 30, 37-39. The output of the read counter portion 7 is 4 bits long.
The reset signal rst is applied to the input terminal 44, and the clock clk is applied to the input terminal 43. The output value of the read counter portion 7 is outputted from the output terminal 45 as the read address.
The output of the NAND gate 42 obtained by NANDing the reset signal rst and the output of the inverter 41 becomes data for the D flip-flop 30. The inverters 40, 41 buffer the output from the D flip-flop 30. One input to each of the AND gates 34-36 is the reset signal rst and the other input to each is the sum output from the corresponding one of the half adders 31-33.
When the reset signal is set at "1," the write counter portion 8 shown in FIG. 8 increases the count starting at "0000" while the read counter portion 7 shown in FIG. 9 increases the count starting at "0001," to implement the first-in first-out operation. Numbers enclosed in "" indicate binary numbers, and "1" corresponds to output of a high level and "0" corresponds to output of a low level.
Next, referring to FIG. 10 and FIG. 11, configurations of the write counter portion 8 and the read counter portion 7 will be described for the case wherein the number of data stored in the FIFO device is not a power of 2. For example, the write counter portion 8 includes a D flip-flop 50, an inverter 51 and an AND gate 52 for dividing the clock clk by 2, a half adder 53 for adding the output of the D flip-flop 50 obtained by dividing the clock clk by 2 and the sum output provided by itself one clock earlier, a half adder 54 for adding the carry output of the half adder 53 and the one-clock-earlier sum output of itself, a half adder 55 for adding the carry output of the half adder 54 and the one-clock-earlier sum output of itself, a D flip-flop 59 for holding the negated sum output of the half adder 53, D flip-flops 60, 61 for respectively holding the sum outputs of the corresponding half adders 54, 55, three AND gates 56-58 for respectively resetting the corresponding D flip-flops 59-61, and an NAND gate 62 and an AND gate 63 for resetting the write counter portion 8 when the count value outputs a certain value, or "1101." The output of the write counter portion 8 is 4 bits long.
The reset signal rst is provided to the input terminal 65 and the clock clk is provided to the input terminal 64. The output value of the write counter portion 8 is outputted from the output terminal 66 as the write address.
All of the AND gates 56-58 are supplied with the output from the AND gate 63 at their respective inputs on one side and with the sum outputs from the corresponding half adders 53-55 at their respective inputs on the other side, and the outputs obtained by ANDing them are inputs to the corresponding D flip-flops 59-61. The D flip-flop 50 receives the output from the AND gate 52 as its input. The output of the AND gate 52 is generated by ANDing the output of the AND gate 63 and the output of the inverter 51. The AND gate 63 outputs the AND of the reset signal rst and the output from the NAND gate 62, and the NAND gate 62 outputs the NAND of the outputs from the D flip-flops 50, 60, 61 and the inverse output of the D flip-flop 59 (a negation of the second-least significant bit in the write address).
The read counter portion 7, for example, includes a D flip-flop 70 and an NAND gate 71 for dividing the clock clk by 2, a half adder 72 for adding the output of the D flip-flop 70 obtained by dividing the clock clk by 2 and the sum output provided by itself one clock earlier, a half adder 73 for adding the carry output of the half adder 72 and the one-clock-earlier sum output of itself, an EXOR gate 74 for outputting the exclusive OR of the carry output of the half adder 73 and the one-clock-earlier output of itself, D flip-flops 80-82 for respectively holding the sum outputs of the corresponding half adders 72, 73 and the output from the EXOR gate 74, and AND gates 76-79 and an NAND gate 75 for resetting the corresponding D flip-flops 80-82. The output of the read counter portion 7 is 4 bits.
When the output value of the read counter portion 7 outputs a certain value, or "1101," the NAND gate 75 outputs "0" to reset the read counter portion 7.
The reset signal rst is applied to the input terminal 84 and the clock clk is applied to the input terminal 83. The output value of the read counter portion 7 is outputted from the output terminal 85 as the read address.
The AND gates 77-79 are all supplied with the output from the AND gate 76 at their respective inputs on one side, and with the sum output from the half adder 72, the sum output from the half adder 73, and the output from the EXOR gate 74 at their respective inputs on the other side. The NAND gate 75 outputs the NAND of the outputs from the D flip-flops 70, 81, 82 and the inverse output from the D flip-flop 80 (a negation of the second-least significant bit in the read address). The output of the NAND gate 71 generated from the NAND of the reset signal rst and the output of the D flip-flop 70 is provided as data for the D flip-flop 70.
As described above, the conventional semiconductor storage device requires two counter portions to implement the FIFO function, which raises the problem that the circuit scale is large.